1. Field of the Disclosure
The present disclosure generally relates to reference voltage generators and, more particularly, to a bandgap reference (BGR) voltage generator circuit with reduced substrate area.
2. Brief Description of Related Art
Reference voltage generators with a minimum (preferably zero) variation of output voltage with temperature are important elements for precise electronics. For example, an analog-to-digital converter (ADC) circuit may be fabricated on the same die with other digital systems increase the integration level. However, to maximize the usability of an ADC operating on sub 1-volt supply voltages, it is desirable to provide an on-chip low-voltage reference generator circuit that can provide a stable reference voltage to the ADC. Reference voltage generators are also used in DRAM's (dynamic random access memory), flash memories, and other analog or digital devices. The generators are required to be stabilized over process, voltage, and temperature variations, and also to be implemented without modification of fabrication process. The increased demand for portable electronic devices and the technology scaling are driving down the supply voltages of digital circuits. Low voltage operation and low power consumption are important design factors for battery-operated portable electronic devices. As CMOS (complementary metal oxide semiconductor) technologies continue to migrate into deep submicron region, the power supply voltage for devices produced using such CMOS technologies will likewise scale to below 1.5V for reliable operation of devices and also to keep the weights of the devices low.
Bandgap reference (BGR) voltage circuits are one of the most popular reference voltage generators that successfully achieves low-power, low-voltage operational demands. BGR circuits are used in bipolar, CMOS and bipolar CMOS (BICMOS) circuit designs for producing stable reference voltages for biasing other circuits on the chip, thereby allowing designs of battery-operated portable electronic devices. The stable reference voltages are used to control other voltage levels within a chip and to provide bias currents that are proportional to absolute temperature. For example, a bandgap reference voltage circuit in a cellular telephone must not only provide the required voltage regulation and bias current, but also must be power efficient because cellular telephones are powered by batteries. As bandgap reference circuits are integral to the majority of today's electronic devices, the reliability of the bandgap reference voltage circuit is essential to avoid device failures.
A conventional bandgap reference circuit is a circuit that subtracts the voltage (VBE) of a forward-biased diode having a negative temperature coefficient from a voltage (VT) proportional to absolute temperature (PTAT) and having a positive temperature coefficient. At room temperature, the temperature coefficient of VBE is −2.2 mV/° C., whereas the temperature coefficient of the thermal voltage VT is +0.086 mV/° C. A PTAT (i.e., VT) can be realized by amplifying the voltage difference of two forward-biased base-emitter junctions. As a consequence, a temperature compensated voltage close to the material bandgap of silicon (˜1.22V) results. Thus, the BGR circuit operates on the principle of compensating the negative temperature coefficient of VBE with the positive temperature coefficient of the thermal voltage VT. A full compensation at room temperature is given by:                               V                      B            ⁢                                                  ⁢            G                          =                                            V              BE                        +                          n              ⁢                                                          ⁢                              V                T                                              =                                    V              BE                        +                          n              ⁢                              kT                q                                                                        (        1        )            where “n” is equal to 25.6 (=2.2/0.086), “k” is Boltzmann's constant (=1.38×10−23 J/K), and “q” is electronic charge (=1.6×10−19 C).
Because the value of VBE at room temperature for low currents is close to 0.650V and VT at room temperature is 25.8 mV the value of VBG (from equation (1) above) is 1.26V. At this point, the temperature dependence of VBG becomes negligibly small. Such a value (=1.26V) is just slightly more than the silicon energy gap (˜1.22V). Therefore, circuits achieving temperature compensation in the range of silicon bandgap are called BGR circuits. As noted before, the output voltage of convention BGR circuits is around 1.26V, which limits the low supply voltage (Vcc) operation. In other words, the operational or supply voltage cannot be lowered below approximately 1.25V, which limits the low-voltage design for the CMOS circuits. Hence, it is desirable to develop a BGR circuit that successfully operates with sub-1V supply voltages.
FIG. 1 illustrates a prior art bandgap reference voltage generator circuit 10 that can operate with sub-1V supply voltage. A detailed description of the circuit 10 along with simulation results is provided in “A CMOS Bandgap Reference Circuit with Sub-1-V Operation” by Banba et al., IEEE Journal of Solid-State Circuits, Vol. 34, No. 5 (May 1999) (hereinafter “Banba”), the description of which is incorporated herein in its entirety. The BGR circuit in FIG. 1 utilizes an operational amplifier 12 along with three PMOS (P-substrate MOS—a type of CMOS) transistors 14 (P1), 16 (P2) and 18 (P3). The source terminals 24, 30 and 36, of transistors P1, P2 and P3 respectively, are electrically connected to a supply voltage Vcc. The gate terminals 26, 32 and 38, of transistors P1, P2 and P3, respectively, are connected to the output 23 of the op-amp 12. The drain terminal 28 of transistor P1 is connected (not shown) to the inverting input 22 of the op-amp 12, thereby supplying voltage Va at input 22. The drain terminal 34 of transistor P2 is connected (not shown) to the non-inverting input 20 of the op-amp 12, thereby supplying voltage Vb at input 20. In other words, transistors P1, P2 and the op-amp 12 are connected in a looped manner. On the other hand, the drain terminal 40 of the transistor P3 is not connected to the op-amp 12, but, instead, functions as an output terminal from which the reference voltage (Vref) generated by the BGR circuit 10 can be obtained. The voltage “Vref” is the same as the voltage “VBG” given in equation (1) above.
It is noted at the outset that the terms “connected” and “electrically connected” are used interchangeably herein. These terms also refer to, in an appropriate context, the condition of being “electrically held at” a given potential. For example, the phrase. “connected to a reference potential” refers to the state of being electrically held at the reference potential.
In the BGR circuit 10, a combination of resistor and diode networks (described later hereinbelow) connected to drains 28 and 34 maintain the op-amp input voltages Va and Vb at the same potential.Va=Vb  (2)As shown in FIG. 1, a resistor 42 (R1) is connected between the drain 28 and a reference potential (or circuit ground); whereas, the anode of a diode 44 is connected to the drain 28 and the cathode of the diode 44 is connected to the reference potential. A resistor-diode network consisting of a resistor 46 (R3) in series with a parallel combination of N diodes 48 is connected between the drain 34 and the reference potential as shown in FIG. 1. It is noted here that for ease of discussion the same reference numeral “48” is used herein to refer to each diode in the N diodes. Another resistor 50 (R2) is connected between the drain 34 and the reference potential, and also in parallel to the resistor-diode network (of R3 and N parallel diodes) as shown in FIG. 1. One terminal of an output resistor 52 (R4) is connected to the drain 40 and the other terminal to the reference potential to provide the reference voltage Vref.
In the circuit 10 in FIG. 1, the resistance of R1 and R2 is the same and the currents I1, I2 and I3 have the same value also.R1=R2  (3)I1=I2=I3  (4)Therefore, the respective branch currents have equal value also.I1a=I2a, I1b=I2b  (5)For the circuit 10 in FIG. 1, the voltage differential, dVf, which is the voltage difference between the forward voltage across diode 44 (Vf1) and the forward voltage across N (N=100 in one implementation in Banba) parallel diodes (Vf2) is given by:dVf=Vf1−Vf2=VT.ln(N)  (6)Banba teaches that the output voltage of the BGR circuit 10 is given by:                               V          ref                =                              R            4                    ⁡                      (                                                            V                  f1                                                  R                  2                                            +                                                d                  ⁢                                                                          ⁢                                      V                    f                                                                    R                  3                                                      )                                              (        7        )            Hence, Vref is determined by the resistance ratio of R2, R3 and R4, and is little influenced by the absolute values of the resistance. Further, in Banba's circuit 10, the transistors P1, P2 and P3 preferably operate in the saturation region so that their drain-to-source voltages can be small when the drain-to-source currents are reduced.
In an experimental analysis of the circuit 10, Banba provides the following values for various resistors in the circuit 10 to achieve a simulated Vcc of 0.84V: R1=R2=2 MΩ, R3=393 kΩ, and R4=884 kΩ. These resistor values provide low power consumption (i.e., current consumption in the range of tens of microamperes). Other resistor values may be selected to achieve results similar to those obtained in Banba. For example, in one implementation, the topology of the circuit 10 in FIG. 1 was fabricated on a silicon substrate using a typical 0.18 μm CMOS fabrication process, with the following resistor values to achieve results similar to those described in Banba: R1=R2=3.2 MΩ, R3=220 kΩ, and R4=800 kΩ. These resistor values were implemented with n-well (on p-substrate) and occupy significant area—the total area of the resistors was 300 μm×300 μm.
Thus, to fabricate a BGR circuit using Banba's circuit con figuration (i.e., the circuit 10 in FIG. 1) with sub 1V supply voltage operation and low power consumption, the substrate area occupied by the resistors in the circuit 10 is approximately 50% of the total silicon bandgap area. In other words, the area of the low voltage, low power bandgap proposed by Banba is dominated by the area of the very high value resistors employed in Banba—50% of the total cell size is due to the area of the resistors employed. Therefore, it is desirable to devise a BGR circuit configuration that achieves sub 1V operation and low power consumption while significantly reducing the chip real estate occupied by the resistors.